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The proposed routing has a greater space for optimization especially for applications with more long-distance traffic.Artificial Neural Network computation relies on intensive vector-matrix multiplications.LDPC codec is also carefully designed to lower the hardware cost by leveraging the systematic-structured parity-check matrix.Then two customized short length LDPC codes--(585,512) and (683,512) augmented from the semi-random parity-check matrix and the A-LLR based asymmetric decoding, are proposed for SLC and MLC designs.Specifically, we propose an optimized FPGA accelerator architecture tailored for bitwise convolution and normalization that features massive spatial parallelism with deep pipelines stages.A key advantage of the FPGA accelerator is that its performance is insensitive to data batch size, while the performance of GPU acceleration varies largely depending on the batch size of the data.Simulation results show that our proposed neural network produces significantly higher inference accuracies than conventional neural network when the synapse devices have nonlinear I-V characteristics.STT-RAM is a promising emerging memory technology in future memory hierarchy. asymmetric bit failure mechanism at different bit flippings, have raised significant concerns in its applications.

However, advanced reverse engineering techniques can physically disassemble the chip and derive the IPs at a much lower cost than the value of IP design that chips carry.

In this paper, we systematically present three techniques for optimizing energy efficiency while maintaining good performance of the proposed LSM neural processors from both an algorithmic and hardware implementation point of view.

First, to realize adaptive LSM neural processors thus boost learning performance, we propose a hardware-friendly Spike-Timing Dependent Plastic (STDP) mechanism for on-chip tuning.

The Journal of Emerging Technologies in Computing Systems invites submissions of original technical papers describing research and development in emerging technologies in computing systems.

Major economic and technical challenges are expected to impede the continued scaling of semiconductor devices.

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Using two different real-world tasks of speech and image recognition to benchmark, we demonstrate that the proposed architecture boosts the average learning performance by up to 2.0% while reducing energy dissipation by up to 29% compared to a baseline LSM design with little extra hardware overhead on a Xilinx Virtex-6 FPGA.